The present invention relates to a frame conversion circuit for demultiplexing various incoming multiplexed signals that have been transmitted over a high-speed communication line and then converting the demultiplexed signals into the same frames thereby making the speeds of the various data signals uniform.
In digital transmission systems, in general, several pieces of information are transmitted after being multiplexed in order to achieve effective use of the transmission medium and greater economy in the transmission. Such multiplexing is performed based on time. One period of the multiplexed signal is called a frame and the multiplexing method is called time-division multiplexing. A plurality of low order group digital signals are time-divisionally multiplexed by a multiplexer into high order group digital signals before transmission over the high-speed communication line. Thus, a greater number of channels are transmitted over the same link. These signals are transmitted from one exchange to another by a suitable transmission means capable of accommodating the necessary number of channels, and thereby transmitted to a destination. Upon arrival at the destination, the high order group digital signals are separated into low order group digital signals by a demultiplexer.
Specifically, in a system like the Integrated Services Digital Network (ISDN), various data such as general data, speech signals, and video signals are transmitted after being multiplexed at different speeds. Therefore, a process for demultiplexing these multiplexed signals with different speeds is required. Hence, a frame conversion circuit adds redundant bits to the lower speed signals, thereby providing them with the same speed as the higher speed signals.
A representative example of prior art frame conversion circuits will be described below with reference to FIG. 1 and FIG. 2. When data (A, B, and C in FIG. 2) are input from a high speed communication line to a tristate buffer 12, the tristate buffer 12 and a tristate buffer 16 are enabled and simultaneously, address signals, generated in a random pattern (3, 1, and 4 in FIG. 2) for indicating addresses at which the data should be written into a memory 11, are output from a write address generator 14. The data are written into the memory according to these address signals. At this time, each random address signal corresponds to a kind of data. Upon completion of the writing of the data into the memory, a tristate buffer 17 is enabled and, at the same time, sequential address signals (1, 2, 3, 4, 5, 6 in FIG. 2) are output from a read address generator 15, and thereupon, data (B, -, A, C, -, - in FIG. 2) are read out from the memory according to these address signals. Here, "-" represents a frame stored in the memory previously or an indefinite frame.
A sign bit adding/checking portion 18 includes a cyclic redundancy check. It adds sign bits to the rearmost position of the data written in the memory, and at the time it monitors the sign bits thereby checking whether the data is properly transmitted and received. By repeating such random writing of data into the memory according to the kinds of data, sequentially addressing the addresses in memory and reading the data from the memory, the frame conversion for arranging various data of different speeds into high speed signals having a uniform speed is performed.
In the above-described conventional frame conversion circuit, when data was written into the memory according to random address signals and, then, sequentially read out, there remained data that had previously been written at the addresses where data was not written this time. Hence, the previous data will also be read out as indicated by oblique lines in FIG. 3. When the read out data are processed in such case, it sometimes occurs that the system becomes unable to recognize the position where the currently processed data is located. In such an event, confirmation of the data is achieved by synchronizing the data by means of the synchronization bits within the frames. But, if old data has remained and the data are by some chance taken as the synchronization bits, then erroneous synchronization or malfunction occurs, which has been a problem in the prior art.
Further, when data are read out from the memory in the initial stage, if there is any address in the memory at which no data was input earlier, the indefinite data read out from the region at that address will be without any sign bits attached thereto, and therefore, errors will be produced when the sign bit is checked as shown in FIG. 4, which has also been a problem in the prior art.